(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving the SiN spacer profile in the process of forming a self-aligned contact opening in the fabrication of integrated circuits.
(2) Description of the Prior Art
The self-aligned contact (SAC) technology has been widely adopted to reduce device area in the fabrication of integrated circuit devices. For example, in forming a SAC for a capacitor between bit lines, the bit lines having silicon nitride spacers on their sidewalls are formed over an insulating layer. A silicon oxide layer covers the bit lines and silicon nitride spacers. A contact opening is etched through the silicon oxide layer to the underlying node contact region. The contact is self-aligned because the silicon nitride spacers are not etched by the silicon oxide etch and thereby form the contact opening.
Typically, a low-pressure furnace deposition is used for the silicon nitride spacer material (LP-SiN) at a temperature of about 800.degree. C. However, for embedded dynamic random access memory (DRAM) devices, it is desirable to reduce the thermal budget to minimize the impact on the titanium silicide in the logic region. Therefore, it is desirable to deposit the silicon nitride spacer material by plasma-enhanced chemical vapor deposition. This presents the problem of how to etch the silicon nitride to form spacers having a good profile.
U.S. Pat. 5,766,992 and 5,731,236, both to Chou et al disclose a PECVD silicon nitride layer etched using SF.sub.6 or CHF.sub.3 to form spacers. U.S. Pat. No. 5,776,832 to Hsieh et al teaches using CHF.sub.3 to etch an opening through a dielectric layer.